FIG. 1 is a circuit diagram of a prior art memory circuit 10. The memory circuit 10 includes a memory array 12 including even and odd rows of floating gate memory cells M4, M6, M8, M10 and M5, M7, M9 and M11, respectively. Switches S2 and S3 select the even and odd rows, respectively, for programming. Each source node of the memory cells is coupled to a source line (SL) to receive a source line voltage during programming, such as 10 V for 0.25 μm memory cells. Bit lines BL0-BL3 are coupled to drain terminals of the transistors of the even and odd row memory cells to provide bit line voltages during programming.
The memory circuit 10 also includes a reference circuit 14 for programming the memory cells M4-M11 of memory array 12. The gate of PM0S transistor M1 is connected to a voltage source Vbias to generate current Ibias. The source, gate and floating gate of each reference cell M2 and M3 are shorted together. When switch S0 is closed, M2 connects to resistor R1. When switch S1 is closed, M3 connects to resistor R1. The node voltage VPWL, which is the word line voltage for programming cells in memory array 12, is determined by the voltage drop across M2 (or M3) and R1 according to the following: VPWL=Vgd(M2)+Ibias×R1 if S0 is on and Vgd(M3)+Ibias×R1 if S1 is on.
The reference circuit 14 of FIG. 1 is utilized in the 0.25 μm technology generation. The circuit generally exhibits good performance, but requires a special floating gate contact 16, which cannot be used with technology generations that utilize self-aligned processes that do not use a mask to define the floating gate (e.g., 0.18 μm generations). The circuit 10 also does not use a common voltage source for the source node of the reference cells of the reference circuit 14 and the source node of the selected memory cells of the memory array 12. The reference cells, therefore, do not exactly track the memory cells, i.e., the programming bias conditions (WL, BL and SL voltages and programming current) of the reference cells are not the same as the memory cells. Consequently, the reference cells cannot completely control memory cell behavior during programming.
FIG. 2 is a circuit diagram of a second prior art memory circuit 20. The memory circuit 20 includes a fixed reference voltage generator circuit 22 that provides a fixed word line voltage to memory array 12. While the voltage circuit 22 does not require a special floating gate contact, the circuit 20 is susceptible to process variations, such as misalignment of polysilicon control gates with the floating gates, and can exhibit a degradation in program efficiency and program disturb immunity therewith. When the threshold voltage of a neighboring cell in the selected bit line is lowers than a memory cell that is to be programmed in the bit line, “punch through” can be made worse, i.e., there may be hot electrons available to program an inhibited, erased cell from the unselected word line. Similarly, when the threshold voltage of a selected cell is higher than the neighboring cell in the same word line, there may be hot electrons available to program the inhibited, erased cell from the neighboring, unselected bit line (referred to as program-ff disturb).
Therefore, there remains a need for a reference circuit scheme that tracks process variations and programming conditions while being compatible with lower feature size processes.